1. Field of the Invention
The present invention relates to a method of correcting data errors of a received digital signal in text broadcasting such as FM multiplex broadcasting and an apparatus for use in the method and, more particularly, to an error correcting method which receives one frame of a digital signal used in, e.g., the DARC (Data Radio Channel) standard, together with a parity code and performs error corrections in both the horizontal and vertical directions
2. Description of the Prior Art
Text information service has been put into practical use in FM multiplex broadcasting in which a digital signal is transmitted by using an idle spectrum region of an FM stereo signal. However, in text information using a broadcast radio wave, many pieces of error information are sometimes contained in the received digital information. Errors of this received digital information are particularly significant upon reception in mobile communication inferior in transmission quality. Therefore, it is necessary to correct errors of the received digital information on the receiving side.
Various systems have been proposed for error correction of this received digital information and the following three systems have been put into practical use as the international standard or the Japanese standard: a DRAC system and a fixed reception system primarily studied in Japan and RDS (Radio Data System) developed in Europe. These three systems are different from each other; i.e., the DARC system uses the product codes of (272,190) codes, the fixed reception system uses (272,190) codes, and the RDS uses (26,16) codes. The DARC system is considered to have a higher error correction accuracy than the other systems. The basic operation of the DARC system, i.e., error correction using the product codes of (272,190) codes will be described below.
In the DARC system, one frame of information is divided into 272 blocks and sequentially transmitted. Each block consists of 272 bits. Each of the first 190 blocks consists of a 16-bit block identification code, 176-bit data, a 14-bit CRC code, and an 82-bit first parity code. Each of the last 82 blocks consists of a 16-bit block identification code, a 190-bit second parity code, and an 82-bit third parity code. The first parity code corresponds to 190 bits of the data and the CRC code of that block, the second parity code corresponds to the data bits and the CRC codes from the first to 190th blocks, and the third parity code corresponds to the first parity codes from the first to 190th blocks.
On the receiving side, as shown in FIG. 1, a data input unit 41 sequentially supplies a signal in units of blocks of 272 bits to an error correcting unit 43. After error correction is performed by using the first and third parity codes, the signal is stored in a frame buffer 44. When the error correcting unit 43 performs error correction, an error signal 42 is output When the frame buffer 44 stores 272 blocks, the first error correction processing is complete. FIG. 2 shows the flow of this first error correction processing. Also, FIG. 3 shows an example of the result of the first error correction processing Each full circle 45 represents a bit still remaining as an error as a result of the first error correction. FIG. 3 shows that a considerable number of errors still remain.
Subsequently, vertical error correction is performed for the signal with the bit array as in FIG. 3 stored in the frame buffer 44. Corresponding bits in the 272 blocks are supplied to the error correcting unit 43, FIG. 1, where vertical error correction is performed by using the second parity code described above. The result is returned to the frame buffer 44. When this processing is sequentially repeatedly performed for the 272 bits (at least 190 bits of data bits and a CRC code), vertical error correction as the second error correction processing is complete. FIG. 4 shows the flow of this second error correction processing, and FIG. 5 shows an example of the result of the second error correction processing. Each open circle 46 represents a bit corrected by the second vertical error correction. Each full circle 47 represents a bit which still remains as an error even after the first and second error corrections. FIG. 5 indicates that as a result of the horizontal and vertical error corrections, a considerable number of error bits are corrected but a few errors still remain.
Accordingly, horizontal error correction is again performed for the signal with the bit array as in FIG. 5 stored in the frame buffer 44. 272 bits of each block are sequentially supplied to the error correcting unit 43, FIG. 1, horizontal error correction is again performed by using the first and third parity codes, and the result is returned to the frame buffer 44. When this processing is sequentially repeatedly performed for the 272 blocks, horizontal error correction again performed as the third error correction processing is complete. FIG. 6 shows the flow of this third error correction processing, and FIG. 7 shows an example of the result of the third error correction processing. Each open circle 49 represents the position of a bit whose error is finally corrected. As a result, all errors are corrected with a very high accuracy.
If, however, the received signal is inferior in quality and contains a large number of errors, error bits which are left uncorrected exist as indicated by full circles 48. If these error bits 48 remain, this frame is discarded and a frame received next is similarly error corrected and output to the screen. Alternatively, as proposed in Japanese Unexamined Patent Publication No. Hei 5-145500, a block in which error bits remain is rewritten with data of a corresponding block received thereafter and is output to the screen. Still another measure is to again receive frame information after 5 seconds or more elapse, perform horizontal error correction for blocks corresponding to blocks (BLK9, BLK11, and BLK264 in FIG. 7) containing error bits, and, if the errors are corrected, output these error-corrected blocks to the screen in place of the preceding blocks (BLK9, BLK11, BLK264 in FIG. 7) in which error bits remain.
As a result of a simulation of this system, the error correction probability when decoding is done by a variable threshold value is about 90% for errors of 11 bits and 30% for errors of 13 bits. When the signal has an 82-bit parity code for 176-bit data, errors up to 11 bits can be corrected with a high accuracy, but the error correction probability for errors more than that is extremely low. The reason for this is as follows. For a predetermined parity code, errors having the number of bits larger than a predetermined number, e.g., 11, cannot be normally corrected, i.e., they are abnormally corrected. This makes the subsequent correction processing using parity check unreliable, so even normal bit data is also rewritten. If normal bit data is thus rewritten, normal data cannot be restored in the subsequent second and third error corrections.
As described above, when a block which cannot be corrected by three error corrections in the horizontal, vertical, and horizontal directions is replaced with a subsequent signal, the processing time is undesirably prolonged. If final error data exists in a final block, the processing time becomes almost twice the processing time when error correction processing is completed by three error corrections.
In the conventional error correcting system, in a signal containing error bits exceeding the error correcting capacity, even normal bit data is also corrected by error correction processing Since this cannot be corrected by the subsequent error correction processing, the correcting capacity is extremely degraded. Also, when this abnormally corrected signal is replaced with a subsequent signal, the time required for a series of error corrections is prolonged. This influence on, e.g., FM multiplex broadcasting is that it takes a very long time to display information or characters on the screen of a liquid crystal display or the like.